The present invention generally relates to methods for making dielectrics for integrated circuit processes and devices. More particularly, the invention relates to multi-level circuit processes, such as damascene processes that utilize metal and metal alloys (e.g., copper and copper alloys) as well as low-k dielectric materials. The methods of the present invention allow for greater control of the dielectric fabrication process.
Built on a semiconducting substrate, integrated circuits comprise of millions of transistors and other devices which communicate electrically with one another and outside packaging material through multiple levels of vertical and horizontal wiring embedded in a dielectric material. Within the multilayer metallization structure, “vias” comprise the vertical wiring, whereas “interconnects” comprise the horizontal wiring. Fabricating the metallization can involve the successive depositing and patterning of multiple layers of dielectric and metal to achieve electrical connection among transistors and to outside packaging material. The patterning for a given layer is often performed by a multi-step process consisting of layer deposition, photoresist spin, photoresist exposure, photoresist develop, layer etch, and photoresist removal on a substrate. Alternatively, the metal may sometimes be patterned by first etching patterns into a dielectric, filling the pattern with metal, then subsequently chemical mechanical polishing the metal so that the metal remains embedded only in the openings of the dielectric. As an interconnect material, aluminum has been utilized for many years due to its high conductivity (and low cost). Aluminum alloys have also been developed over the years to improve the melting point, diffusion, electromigration and other qualities as compared to pure aluminum. Spanning successive layers of aluminum, tungsten has traditionally served as the conductive via material. Silicon dioxide (dielectric constant of around 4.0) has been the dielectric of choice, used in conjunction with aluminum-based and tungsten-based interconnects and via for many years. The drive to faster microprocessors and more powerful electronic devices in recent years has resulted in very high circuit densities and faster operating speeds, which in turn have required higher conductivity metals and lower-k dielectrics (preferably below 3.0, more preferably below 2.5 dielectric constant). In the past few years, VLSI (and ULSI) processes have been moving to copper damascene processes where copper (or copper alloys) is used for the higher conductance in the conductor lines and spin-on or CVD low-k dielectrics are used for the insulating material surrounding the conductor lines. To circumvent problems with etching, copper along with a barrier metal is blanket deposited over recessed dielectric structures consisting of interconnect and via openings and subsequently polished in a processing method known as “dual damascene.” The bottom of the via opening is usually the top of an interconnect from the previous metal layer or in some instances, the contacting layer to the substrate.
FIG. 1 gives an example of a typical process for patterning a dielectric film. First a dielectric layer film 12 is deposited on a wafer substrate 10 typically by spin-on or chemical vapor deposition processes. Next, a removable, photosensitive “photoresist” film 14 is spun onto the wafer substrate 10. Afterward, the photoresist 12 is selectively exposed through a mask which serves as a template for the layer's circuit pattern and is subsequently developed (developer applied to remove either exposed or unexposed areas depending upon the type of resist). The photoresist is typically baked after spin, exposure, and develop. Next, the layer film is etched in a reactive plasma, wet bath, or vapor ambient in regions not covered by the photoresist to define the circuit pattern. Lastly, the photoresist 14 is stripped. The process of layer deposition, photoresist delineation, etching, and stripping is repeated many times during the fabrication process.
Because photoresist may unacceptably erode during the etch process or may not be able to be adequately delineated within device specifications, a hard mask is sometimes inserted between the layer film and the photoresist (the materials of the invention could also be used for making such a hard mask). FIG. 2 illustrates this typical method, which is similar to the dielectric patterning process described previously in relation to FIG. 1. The layer film could be metal, semiconductor, or dielectric material depending on the application. As can be seen in FIG. 2, a substrate 10 is provided on which is deposited a layer film 12. On film 12 is deposited a hard mask 13. On hard mask 13 is deposited a photoresist material 14. The photoresist is exposed and developed so as to selectively expose the underlying hard mask 13. Then, as can be further seen in FIG. 2, the hard mask 13 is etched via the exposed areas in photoresist 12. Thereafter, the photoresist is removed and the dielectric film 12 is etched by using the hard mask 13 as the pattern mask.
The “dual damascene” process used in integrated circuit application combines dielectric etches and sometimes hard masks to form trenches and vias to contain metal interconnects. FIG. 3 demonstrates one implementation of the technique. From the bottom up in FIG. 3a, the stack is made up of a substrate 20, a dielectric film 22, a hard mask 23, a second dielectric film 24, and a patterned photoresist layer 26. After etching and photoresist strip, a dual-width trench feature is formed as shown in FIG. 3b. The openings are then filled with metal and subsequently polished, leaving metal only within the openings.
The procedures shown in FIGS. 1-3 are often repeated many times during integrated circuit application, which adds to the cost of the circuit and degrades yield. Reducing the number of steps, such as implementing a photopatternable dielectric material which obviates the need for photoresist and etching steps, has huge benefits to the circuit manufacturer.
In addition to the dielectric IC material being photopatternable, it is also desirable that the material be easy to deposit or form, preferably at a high deposition rate and at a relatively low temperature. Once deposited or formed, it is desirable that the material be easily patterned, and preferably patterned with small feature sizes if needed. Once patterned, the material should preferably have low surface and/or sidewall roughness. It might also desirable that such materials be hydrophobic to limit uptake of moisture (or other fluids), and be stable with a relatively high glass transition temperature (not degrade or otherwise physically and/or chemically change upon further processing or when in use).
There is a need for improved methods of making dielectric materials. There is a further need for improved methods of making dielectric materials